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Critical-Bitstream-Based SEU Injection and Validation for Xilinx SRAM-Based FPGAs

Tingting Yu, Lei Chen, Xuewu Li, Shuo Wang, and Jing Zhou
Beijing Microelectronics Technology Institute, Beijing, P. R. China

Abstract—SEU (Single Event Upset) injection system implemented in a single FPGA always suffers difficulties of partitioning circuit modules and obtaining target bitstream. This paper presents a critical-bitstream localization strategy to find out the injection target for Xilinx FPGAs. Two assumptions are proposed to obtain frame addresses and bit offsets of the critical bitstream corresponding to CUT (circuit under test). To verify the localization strategy, a SEU injection framework is also introduced. Experimental results on XQ5VLX110t show that 2977 bits are identified as critical bits and among them 343 bits are judged as SEU sensitive ones. While the process of random injection only finds 97 SEU sensitive bits. Comparing the data, the fault rate of the critical-bits injection is 52.8% higher than that of the random-bits injection. That indicates the proposed localization strategy is effective.

Index Terms—SEU injection, critical Bitstream, placement constraints, precise localization, FPGA

Cite: Tingting Yu, Lei Chen, Xuewu Li, Shuo Wang, and Jing Zhou, "Critical-Bitstream-Based SEU Injection and Validation for Xilinx SRAM-Based FPGAs," International Journal of Electrical Energy, Vol. 5, No. 1, pp. 29-33, June 2017. doi: 10.18178/ijoee.5.1.29-33

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