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Low Power Testing of VLSI Circuits Using Test Vector Reordering

A. M. Sudha
Department of Electrical and Electronics Engineering, Bannari Amman Institute of Technology, Sathyamangalam, TN, India

Abstract—Power consumption is one of the biggest challenges in high performance VLSI design and testing. Low power VLSI circuits dissipate more power during testing when compared with that of normal operation. Dynamic power has been the dominant part of power dissipation in CMOS circuits, however, in future technologies the static portion of power dissipation will outreach the dynamic portion. The proposed approach is based on a reordering of test vectors in the test sequence to minimize the average and peak power of the circuit using test application. In this paper weighted switching activity is derived based on the average power consumed in the logic gates during all possible event conditions. Since this weighted switching activity is based on the power, the proposed method gives more accurate results. The proposed algorithm is implemented and verified using ISCAS85 benchmark circuits. Power is estimated for the circuits using Tanner EDA tool. The results show that power is reduced significantly over the existing methods.

Index Terms—weighted switching activity, test power, reordering, power dissipation, power matrix

Cite: A. M. Sudha, "Low Power Testing of VLSI Circuits Using Test Vector Reordering," International Journal of Electrical Energy, Vol. 2, No. 4, pp. 284-288, December 2014. doi: 10.12720/ijoee.2.4.284-288

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